Disk driving device selectively using delayed step pulses

ABSTRACT

A disk driving device is provided with a stepping motor arranged to move a head in units of a predetermined step with respect to a disk-shaped recording medium and a driving pulse generating circuit arranged to generate driving pulses for driving the stepping motor on the basis of a step pulse signal supplied from a host computer. The driving pulse generating circuit is arranged such that, the driving pulse generating circuit outputs, to the stepping motor, driving pulses obtained by delaying, by a predetermined length of time, step pulses occurring sequentially in the step pulse signal, if the step pulse signal is supplied at intervals of time less than a predetermined period of time, and outputs, to the stepping motor, driving pulses obtained without delaying the step pulse signal if the step pulse signal is supplied at intervals of time not less than the predetermined period of time.

This is a continuation application under 37 CFR 1.62 of priorapplication Ser. No. 08/185,597, filed Jan. 24, 1994, now abandoned.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a disk driving device and more particularly toa head feeding arrangement which is advantageous for the disk drivingdevice.

2. Description of the Related Art

A stepping motor has heretofore been employed as a drive source forfeeding a head in a disk driving device such as a floppy disk drivingdevice. In performing a so-called seek action, the head is moved to adesired recording track on a disk by driving the stepping motor withdriving pulses which are generated according to a step pulse signalsupplied for moving the head from outside, for example, from a hostcomputer or the like.

However, if the pulse interval, or a step rate, of the step pulse signalfrom the host computer becomes short, the stepping motor becomesincapable of following the step pulse signal any longer. In such a case,there arises an incident wherein the head fails to reach the desiredtrack. Hereinafter this failure will be called a misseek. The misseekresults from a build-up delay of the action of a mechanical part to beperformed in response to the step pulse signal, due to static friction,inertia, mechanical backlash or play, etc., of a carriage on which thehead is mounted, the stepping motor and a mechanism arranged to transmitthe driving force of the stepping motor to the carriage.

During recent years, the disk driving device has become thinner in shapeand compact in size. As a result, the size of the stepping motor alsohas become smaller. The driving force becomes smaller accordingly as thesize of the stepping motor is reduced. The size of the mechanism fortransmitting the driving force of the stepping motor to the carriage isalso reduced for cost reduction. The reduction in size and cost has beendisadvantageous in respect to accuracy and has brought about a tendencyof increasing the build-up delay of the action mentioned above. Thetendency becomes stronger depending on the environment particularly at alow ambient temperature. Further, in a case where the disk drivingdevice is arranged to perform a driving action with a battery, theabove-stated problem is apt to be brought about by a decrease in torqueof the stepping motor resulting from a low voltage and batteryconsumption.

The above-stated misseek takes place sometimes for a step pulse signalof a step rate between 2.5 msec and 3 msec which is often adopted inmanufactured products. The occurrence of such a misseek is undesirablewith respect to reliability of recording or reproduction.

The reason why a build-up delay of the seek action causes a misseek in acase where the step rate is short is believed to be as follows. When thestep pulse signal is supplied while the carriage, the stepping motor,etc., are quiescent, the stepping motor is not brought to an expectedstable position by the excitation of the stepping motor driver inresponse to the first step pulse of the step pulse signal before asucceeding step pulse is supplied. In other words, the head has not beenmoved to a desired track when the succeeding step pulse is supplied. Asa result, the excitation phase of the stepping motor driver is shiftedby the succeeding, or second, step pulse while the stepping motor stillremains in an unstable position. Under such a condition, the head cannotbe moved to the desired track, thereby causing a misseek, because thetorque of the stepping motor decreases to lower the speed of the headmoving action, and the head is thus brought to a wrong place.

SUMMARY OF THE INVENTION

This invention is directed to the solution of the problem mentionedabove. It is, therefore, a first object of this invention to provide adisk driving device which is capable of accurately following a steppulse signal supplied from a host computer.

It is a second object of this invention to provide a disk driving devicewhich is capable of moving a head accurately to a desired track, withoutcausing any misseek, even in the event of changes in the step rate of astep pulse signal supplied from a host computer.

It is a third object of this invention to provide a computer systemwhich is capable of preventing occurrence of a misseek by enhancing thestep pulse signal following occurrence thereof and by causing a head toreach a desired track without fail even if the pulse interval of a steppulse signal supplied becomes short.

To attain these objects, a disk driving device which is arranged as apreferred embodiment of this invention is provided with head drivingmeans for moving a head in units of a predetermined step with respect toa disk-shaped recording medium, and driving pulse generating means forgenerating driving pulses for actuating the head driving means on thebasis of an externally supplied step pulse signal, the driving pulsegenerating means being arranged to output, to the head driving means,driving pulses obtained by delaying the step pulse signal by apredetermined length of time, if the step pulse signal is supplied atintervals of time less than a predetermined period of time.

Further, to attain the objects, a disk driving device which is arrangedas a preferred embodiment of this invention is provided with headdriving means for moving a head in units of a predetermined step withrespect to a disk-shaped recording medium, and driving pulse generatingmeans for generating driving pulses for driving the head driving meanson the basis of an externally supplied step pulse signal, the drivingpulse generating means being arranged to output, to the head drivingmeans, driving pulses obtained by delaying, by a predetermined length oftime, step pulses occurring sequentially in the step pulse signal, ifthe step pulse signal is supplied at intervals of time less than apredetermined period of time, and to output, to the head driving means,driving pulses obtained without delaying the step pulse signal if thestep pulse signal is supplied at intervals of time not less than thepredetermined period of time.

Further, a preferred embodiment of this invention is a computer systemwhich includes the above-stated disk drive device as a built-in partthereof.

It is a fourth object of this invention to provide a disk controlintegrated circuit which is arranged to perform the functions mentionedabove.

These and other objects and features of this invention will becomeapparent from the following detailed description of an embodimentthereof taken in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing the arrangement of the head drivingcontrol circuit of a disk driving device arranged according to thisinvention.

FIGS. 2(a) to 2(i) show a timing chart explaining the operation of thecircuit shown in FIG. 1.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

A disk driving device according to this invention is described in detailbelow through its embodiment with reference to the drawings, whereinFIG. 1 shows in a block diagram the arrangement of the disk drivingdevice of this invention and FIGS. 2(a) to 2(i) show in a chart thetiming of each of signals related to the head moving operation of thedisk driving device.

Referring to FIG. 1, a microprocessor 100 is arranged as a host computerin a computer system in which the disk driving device of this inventionis built or to which the disk driving device of this invention isconnected. The arrangement includes a keyboard 101, a monitor display102, a printer 103 and a memory 104 which consists of a ROM and a RAM.The arrangement of the disk driving device for driving a floppy disk orthe like is composed of elements other than the elements 100 to 104. Acircuit arrangement shown within a block DIC in FIG. 1 is unitized in anIC.

Referring to FIG. 1, a step pulse signal STEP for moving a head issupplied from the host computer 100 which is connected to the diskdriving device. A clock pulse signal CLK is supplied from a clockoscillator (not shown) which is disposed within the disk driving device.A power-on-reset signal POR is supplied when a power supply is turnedon.

A delay circuit 1 is arranged to receive the step pulse signal STEPwhich is supplied from the host computer 100 by a negative logic, in thecase of this embodiment as shown in FIG. 2(a), and forms a delayed steppulse signal of negative logic by delaying the step pulse signal STEP bya predetermined length of time t1, as shown in FIG. 2(b). A counter 2counts the pulses of the clock pulse signal CLK which is supplied fromthe clock oscillator, as shown in FIG. 2(f). The counter 2 is arrangedto be reset by the low level of the step pulse signal STEP of FIG. 2(a),and to output a pulse of positive logic if the step pulse signal STEP ofFIG. 2(a) is not supplied for a period of at least 5.5 msec (how to setthis period of time will be described later herein). When the pulse ofpositive logic is outputted from the counter 2, a flip-flop 3 is resetthrough an OR circuit 9 at a timing point e2 as shown in FIG. 2(e).

The flip-flop 3 is arranged to be reset by the output of the OR circuit9, as shown in FIG. 2(e). The +Q output of the flip-flop 3 is set at ahigh level, as shown in FIG. 2(c), and its -Q output at a low level, asshown in FIG. 2(d), by the rear edge of the delayed step pulse signal ofFIG. 2(b) which is obtained by delaying the step pulse signal STEP ofFIG. 2(a) by the predetermined length of time t1. A multiplexer 4 isarranged to selectively supply, as its output signal shown in FIG. 2(g),either the step pulse signal STEP of FIG. 2(a) or the delayed step pulsesignal of FIG. 2(b) according to the output signals of the flip-flop 3shown in FIG. 2(c) and FIG. 2(d). A driver control circuit 5 controls,on the basis of the step pulse signal of FIG. 2(g) which is suppliedfrom the multiplexer 4, a driver 6 which is arranged to generatestepping motor driving pulses for driving a stepping motor 7.

A transmission mechanism 8 is arranged in a known manner to transmit thedriving force of the stepping motor 7 to a carriage 11 on which a head12 arranged to perform writing and reading is mounted. A disk-shapedrecording medium 10 is subjected to a predetermined formatting. In FIG.1, reference symbols Tr0, Tr1,-.-.-.-, TrN denote the positions oftracks formed on the recording medium 10. Reference symbol (i) denotesdirections in which the head 12 mounted on the carriage 11 is to bemoved. The track positions of the head 12 are also shown in FIG. 2(i).

The disk driving device of this invention which is arranged as describedabove operates as follows.

When a power supply is turned on on the side of the host computer whichis connected to the disk driving device, the power supply of the diskdriving device also turns on at the same time. The level of thepower-on-reset signal POR become high to reset the delay circuit 1. Theflip-flop 3 is also reset through the OR circuit 9, at the point of timee1 as shown in FIG. 2(e). As a result, the level of the output of thedelay circuit 1 becomes high. The level of the +Q output of theflip-flop 3 becomes low and that of the -Q output of the flip-flop 3high.

After completion of resetting, the level of the power-on-reset signalPOR becomes low. The clock pulse signal CLK begins to oscillate. Thedelay circuit 1 and the counter 2 come to assume a standby stateawaiting the arrival of the step pulse signal STEP of FIG. 2(a) from thehost computer 100. The flip-flop 3 assumes a standby state awaiting thedelayed step pulse signal of FIG. 2(b) from the delay circuit 1.

When the first step pulse, which is shown at a point a1 in FIG. 2(a), issupplied from the host computer 100, the multiplexer 4 selects andoutputs to the driver control circuit 5 the step pulse a1 shown in FIG.2(a), because the +Q and -Q outputs of the flip-flop 3 respectivelyremain at a low level and at a high level with the flip-flop 3 in itsreset state, as shown in FIGS. 2(c) and 2(d). The driver control circuit5 then outputs and supplies a driver driving signal to the driver 6. Thedriver 6 outputs a stepping motor excitation phase signal as shown inFIG. 2(h). The stepping motor 7 is driven by this signal.

The carriage 11 is driven through the driving force transmissionmechanism 8. The head 12 begins to move to a desired track on therecording medium 10. While the movement of the head 12 is describedherein to cover only its radially inward movement from the track Tr0 ofthe formatted recording medium for the sake of simplification ofdescription, the embodiment is of course capable of moving the head 12from any desired position on the recording medium in any directionwithout restrictions.

When the step pulse a1 is inputted, the inertia of the stepping motor 7,that of the carriage 11, the mechanical backlash or play of thetransmission mechanism 8, etc., cause the head 12, i.e., the carriage11, to actually begin to move after a delay time t1 at a point P0 asshown in FIG. 2(i). The delay time t1 of the delay circuit 1 is set atsuch a value that approximately corresponds to the build-up delay due tothe inertia, backlash or play, etc., existing between the stepping motor7 and the carriage 11.

As the first step pulse a1 is supplied from the host computer 100 to thedelay circuit 1, a step pulse b1 is formed by delaying the first steppulse a1 by the length of time t1 as shown in FIG. 2(b). By the rearedge of the delayed step pulse b1, the +Q output of the flip-flop 3 isset at a high level, and the -Q output of the flip-flop 3 is set at alow level, so that the state of the multiplexer 4 changes from the stateof selecting, as its output shown in FIG. 2(g), the step pulse signalSTEP shown in FIG. 2(a) to a state of selecting the delayed step pulsesignal outputted from the delay circuit 1 as shown in FIG. 2(b).

Meanwhile, the counter 2 is reset when each step pulse of the step pulsesignal STEP of FIG. 2(a) is inputted to its reset terminal RST andbegins to count the pulses of the clock pulse signal CLK. In a casewhere a next step pulse of the step pulse signal STEP of FIG. 2(a) isnot inputted within a predetermined period of time t3, the output levelof the counter 2 becomes high. (In the case of this embodiment, theperiod of time t3 is set at 5.5 msec. This value represents a period oftime during which the stepping motor in the disk driving device isexpected to be caused by the step pulse to move the head to a desiredposition and to come to a stop. This period of time is considered suchthat, the build-up delay t1 of the stepping motor takes place relativeto the first step pulse coming from the host computer 100 after thelapse of the period of time t3. The period of time t3 varies with thedisk driving device in use). With the output level of the counter 2becoming high, the flip-flop 3 is reset through the OR circuit 9. As aresult, the multiplexer 4 comes to resume the state of selecting thestep pulse signal STEP of FIG. 2(a) which comes directly from the hostcomputer 100 without passing through the delay circuit 1.

In a case where the pulse interval of the step pulse signal STEPsupplied from the host computer 100 is so short that, after the firststep pulse al is inputted, the second step pulse a2 of the step pulsesignal STEP is inputted when the head 12 comes to a position P1 halfwayin its movement from the track Tr0 to a next track Tr1, as shown in FIG.2(i), i.e., at a point of time obtained when a period of time t2 haselapsed from the first step pulse a1, the head 12 fails to be caused toreach the desired track Tr1 by then as expected in response to the firststep pulse a1, due to the delay time t1 of the start of the head movingaction. Then, the stepping motor 7 assumes an unstable position andfails to reach a stable position relative to the excitation phase shownin FIG. 2(h).

Therefore, under such a condition, if the second step pulse a2 issupplied as it is while the head 12 is at the position P1, as in thecase of the conventional disk driving device described in the foregoing,the stepping motor 7 does not adequately act and the head 12 might cometo a stop before reaching the desired track position.

To solve this problem, the disk driving device according to thisinvention operates as follows. In a case where the second step pulse a2is supplied by the timing of having the head 12 at the position P1between the tracks Tr0 and Tr1, the interval t2 between the step pulsesa1 and a2 supplied from the host computer 100 is less than 5.5 msec. Atthat point of time, therefore, the flip-flop 3 has not been reset, and adelayed step pulse b2 which is obtained by delaying the step pulse a2 bythe length of time t1 is outputted from the multiplexer 4 as its output(g), as indicated by a pulse g2 in FIG. 2(g).

The pulse g2 outputted from the multiplexer 4 is delayed as much as thelength of time t1 corresponding to the action delay time of the head 12from the second step pulse a2 as mentioned above. By the time the pulseg2 is outputted, therefore, the head 12 has reached a position P2 at thetrack Tr1. Both the stepping motor 7 and the head 12 have reached theirdesired track positions by then as expected to be moved in response tothe first step pulse al.

Therefore, the output of the driver control circuit 5 is varied by thepulse g2. The stepping motor 7 then drives the head 12 according to theexcitation phase output (h) of the driver 6. The head 12 is thus movedfrom the track Tr1 to the track Tr2. At the position P2, the steppingmotor 7, the driving force transmission mechanism 8 and the carriage 11are at their desired positions and in their operating states. Therefore,without the delay for the length of time t1, the head 12 can be smoothlymoved to the track Tr2, and the operation can be also smoothly performedfor a next pulse g3 which is based on the third delayed step pulse b3.

In a case where the interval between the third step pulse a3 and a nextstep pulse a4 is more than 5.5 msec as shown in FIG. 2(a), that is, ifno step pulse is inputted from the host computer 100 for a certainperiod of time, the head 12 has already been moved to the track Tr3 asexpected from the step pulse a3. Further, in this case, the steppingmotor 7, the carriage 11 and the driving force transmission mechanism 8might be already at rest after having finished their actions. In view ofthis, as shown in FIG. 2(e), the flip-flop 3 is reset by the signal e2outputted from the counter 2 by counting 5.5 msec. Then, the step pulsesbeginning with the fourth step pulse a4 shown in FIG. 2(a) begin to beprocessed in the same manner as the first step pulse a1. The step pulsea4 is supplied as it is to the driver control circuit 5, as a pulse g4,without delaying it. For the fifth step pulse a5 which is inputted aperiod of time t2 after the step pulse a4, a delayed step pulse b5 issupplied to the driver control circuit 5 as a pulse g5.

Further, if an interval t4 between the fifth step pulse a5 and the sixthstep pulse a6 and an interval t4 between the sixth step pulse a6 and theseventh step pulse a7 are more than 5.5 msec, that is, if a state ofreceiving no step pulse from the host computer 100 for a certain periodof time continues, the flip-flop 3 is reset by the output e3 of thecounter 2, shown in FIG. 2(e), after the lapse of 5.5 msec from the steppulse a5. Then, the sixth step pulse a6 is supplied, without delaying itin the same manner as the first step pulse a1, to the driver controlcircuit 5 as a pulse g6. For the seventh step pulse a7, a pulse g7 issupplied to the driver control circuit 5 in exactly the same manner asthe step pulse a6.

The stepping motor 7 and the head 12 then act as follows. By the timewhen the pulse g6 is supplied to the driver control circuit 5, thestepping motor 7 and the head 12 have already reached a position P4 (forthe track Tr5) expected to be attained in response to the step pulse a5,i.e., the pulse g5. They might be quiescent by then.

In this instance, the action to be performed in response to the pulse g6begins at the end of the delay time t1. The pulse g7 is supplied to thedriver control circuit 5 after the lapse of an interval which is atleast 5.5 msec. This time interval is sufficiently long for allowing thehead to reach a track position P5 (at the track Tr6) to which the head12 is expected to be moved in response to the step pulse a6, i.e., thepulse g6. The step pulse a7, therefore, does not have to be delayed andis outputted without delay as the pulse g7.

As described above, in a case where the step pulse signal from the hostcomputer 100 continues at intervals of time longer than a certain periodof time, each of the step pulses is outputted as the first step pulse,without delaying it, to the driver control circuit 5.

In accordance with the method described above, in a case where the headis quiescent or nearly quiescent with no step pulse inputted for aperiod of time longer than a predetermined period of time, a seek actioncan be accurately accomplished without a drop in the operating speed ofthe stepping motor, or movement to a wrong position, which otherwiseresults from the fact that the stepping motor and the head fail to reachtheir positions to which they are expected to have been moved inresponse to the first step pulse when the second step pulse is inputted,due to a delay time after the stepping motor is driven and beforecommencement of the action of the carriage on which the head is mounted.

The embodiment described above is arranged in such a manner that, in acase where the step pulse signal is supplied from the host computer atintervals of time less than a predetermined period of time, a delayedpulse signal is formed by delaying a second and subsequently occurringstep pulses as much as a delay time required before commencement ofaction after the stepping motor is driven. It is possible to set thedelay time for each of the step pulses to be delayed by individuallyobtaining a difference in time between the input of the second steppulse from the host computer and arrival of the head at a position towhich the head is expected to be moved in response to the first steppulse. This method permits smoother execution of a seek action as thesupply of the delayed step pulses enables the stepping motor and thehead to always reach their positions expected to be reached in responseto a preceding step pulse even if the pulse interval of the pulse signalhappens to vary.

Further, the circuit DIC in this embodiment which consists of the delaycircuit 1, the counter 2, the flip-flop 3, the multiplexer 4, etc., asshown in FIG. 1, is formed together with other circuits into a one-chipIC as a disk driving control IC.

As described above, the embodiment is capable of smoothly moving thehead by solving the problem that the delayed start of a stepwise drivingaction due to inertia, static friction and backlash or play of thestepping motor, the carriage and the transmission mechanism brings thestepping motor into an unstable state to prevent the head from reachinga desired track in response to the input of a step pulse. Unlike theconventional device, the embodiment never brings about such aninconvenience that, after the first or initial step pulse is suppliedfor driving the stepping motor, a successor step pulse is suppliedbefore the end of the period of time of a mechanical delay caused by thebacklash or play of the transmission mechanism, etc., to prevent drivingto a desired track. The arrangement of the embodiment thus enables thehead moving control to be always accurately, reliably and smoothlycarried out even in a case where the pulse interval of the step pulsesignal becomes short.

What is claimed is:
 1. A disk driving device comprising:a) head drivingmeans for moving a head in units of a predetermined step with respect toa disk-shaped recording medium, said head driving means including astepping motor; b) driving pulse generating means for generating drivingpulses for actuating said head driving means on the basis of anexternally supplied step pulse signal comprising a plurality of pulses,wherein said driving pulse generating means is arranged to input to saidhead driving means at least one driving pulse obtained by delaying apulse of the step pulse signal by a predetermined length of time lessthan a predetermined period of time, if pulses of the step pulse signalare supplied at intervals of time less than a predetermined period oftime, wherein the externally supplied step pulse signal is supplied by acomputer device to which said disk driving device is connected, andwherein said driving pulse generating means is arranged also to generatedriving pulses corresponding to pulses of the step pulse signal and toinput the so generated driving pulses to said head driving means andsaid driving pulse generating means is arranged to selectively input tosaid head driving means, according to intervals of pulses in the steppulse signal, either driving pulses obtained without delaying pulses ofthe step pulse signal or driving pulses obtained by delaying pulses ofthe step pulse signal by the predetermined length of time.
 2. A deviceaccording to claim 1, wherein said driving pulse generating means isarranged to input to said head driving means driving pulses obtained bydelaying, by the predetermined length of time, pulses occurringsequentially in the step pulse signal if pulses of the step pulse signalare supplied at intervals of time less than the predetermined period oftime.
 3. A device according to claim 2, wherein said head is mounted ona head carriage which is movable in a radial direction of thedisk-shaped recording medium and is arranged to be driven by saidstepping motor, and wherein the predetermined length of time to be usedfor delaying corresponds to a length of time of a delay resulting fromat least one of inertia, backlash and play existing within a part of thedisk driving device extending from said stepping motor through saidcarriage.
 4. A device according to claim 2, wherein the predeterminedperiod of time corresponds to a length of time necessary for said headcomes to a quiescent state after a pulse in said step pulse signalcauses the head to move from a track at which the head is currentlylocated to an adjacent track on the disk-shaped recording medium.
 5. Adevice according to claim 2, wherein said driving pulse generating meansincludes a delay circuit for delaying said at least one pulse of thestep pulse signal, a counter for deciding whether or not a pulseinterval of the step pulse signal is less than the predetermined periodof time, and a multiplexer arranged to selectively perform switching,according to an output of said counter, between a driving pulse obtainedwithout delaying a pulse of the step pulse signal and a driving pulseobtained through said delay circuit by delaying a pulse of the steppulse signal by the predetermined length of time.
 6. A disk drivingdevice comprising:a) head driving means for moving a head in units of apredetermined step with respect to a disk-shaped recording medium; andb) driving pulse generating means for generating driving pulses foractuating said head driving means on the basis of an externally suppliedstep pulse signal comprising a plurality of pulses, wherein said drivingpulse generating means is arranged to input to said head driving meansdriving pulses obtained by delaying, by a predetermined length of time,step pulses occurring sequentially in the step pulse signal, if pulsesof the step pulse signal are supplied at intervals of time less than apredetermined period of time, and to input to said head driving meansdriving pulses obtained without delaying pulses in the step pulse signalif pulses of the step pulse signal are supplied at intervals of time notless than the predetermined period of time.
 7. A device according toclaim 6, wherein said head driving means includes a stepping motor.
 8. Adevice according to claim 7, wherein the externally supplied step pulsesignal is is supplied by a computer device to which said disk drivingdevice is connected, and wherein said driving pulse generating means isarranged also to generate undelayed driving pulses in accordance withthe step pulse signal.
 9. A device according to claim 7, wherein saidhead is mounted on a head carriage which is movable in a radialdirection of the disk-shaped recording medium and is arranged to bedriven by said stepping motor, and wherein the predetermined length oftime to be used for delaying corresponds to a length of time of a delayresulting from at least one of inertia, backlash and play existingwithin a part of the disk driving device extending from said steppingmotor through said carriage.
 10. A device according to claim 7, whereinthe predetermined period of time corresponds to a length of timenecessary for said head comes to a quiescent state after a pulse in saidstep pulse signal causes the head to move from a track at which the headis currently located to an adjacent track on the disk-shaped recordingmedium.
 11. A device according to claim 7, wherein said driving pulsegenerating means includes a delay circuit for delaying pulses of thestep pulse signal, a counter for deciding whether or not a pulseinterval of the step pulse signal is less than the predetermined periodof time, and a multiplexer arranged to selectively perform switching,according to an output of said counter, between a driving pulse obtainedwithout delaying a pulse of the step pulse signal and a driving pulseobtained through said delay circuit by delaying a pulse of the steppulse signal by the predetermined length of time.
 12. A computer systemcomprising:a) a host computer; b) head driving means for moving a headin units of a predetermined step with respect to a disk-shaped recordingmedium; and c) driving pulse generating means for generating drivingpulses for actuating said head driving means on the basis of a steppulse signal supplied from said host computer and comprising a pluralityof pulses, wherein said driving pulse generating means is arranged toinput to said head driving means driving pulses obtained by delaying, bya predetermined length of time, pulses occurring sequentially in thestep pulse signal, if pulses of the step pulse signal are supplied atintervals of time less than a predetermined period of time, and to inputto said head driving means driving pulses obtained without delayingpulses of the step pulse signal if pulses of the step pulse signal aresupplied at intervals of time not less than the predetermined period oftime.
 13. A system according to claim 12, wherein said head drivingmeans includes a stepping motor.
 14. A system according to claim 13,wherein said head is mounted on a head carriage which is movable in aradial direction of the disk-shaped recording medium and is arranged tobe driven by said stepping motor, the predetermined length of time to beused for delaying corresponds to a length of time of a delay resultingfrom at least one of inertia, backlash and play existing within a partextending from said stepping motor through said carriage, and thepredetermined period of time corresponds to a length of time necessaryfor said head comes to a quiescent state after a pulse in said steppulse signal causes the head to move from a track at which the head iscurrently located to an adjacent track on the disk-shaped recordingmedium.
 15. A system according to claim 13, wherein said driving pulsegenerating means includes a delay circuit for delaying pulses in thestep pulse signal, a counter for deciding whether or not a pulseinterval of the step pulse signal is less than the predetermined periodof time, and a multiplexer arranged to selectively perform switching,according to an output of said counter, between a driving pulse obtainedwithout delaying a pulse of the step pulse signal and a driving pulseobtained through said delay circuit by delaying a pulse of the steppulse signal by the predetermined length of time.
 16. A head drivecontrol integrated circuit comprising:a) head driving means for moving ahead in units of a predetermined step with respect to a disk-shapedrecording medium, said head driving means is arranged to drive astepping motor; and b) driving pulse generating means for generatingdriving pulses for actuating said head driving means on the basis of anexternally supplied step pulse signal comprising a plurality of pulses,wherein said driving pulse generating means is arranged to input to saidhead driving means driving pulses obtained by delaying, by apredetermined length of time, pulses occurring sequentially in the steppulse signal if pulses of the step pulse signal are supplied atintervals of time less than a predetermined period of time, wherein theexternally supplied step pulse signal is supplied by a computer deviceto which said integrated circuit is connected, and wherein said drivingpulse generating means is arranged also to generate driving pulsescorresponding to pulses of the step pulse signal and to input the sogenerated driving pulses to said head driving means and said drivingpulse generating means is arranged to selectively input to said headdriving means, according to a pulse interval of the step pulse signal,either driving pulses obtained without delaying pulses of the step pulsesignal or driving pulses obtained by delaying pulses of the step pulsesignal and, if pulses of the step pulse signal are supplied at intervalsof time less than the predetermined period of time, said driving pulsegenerating means inputs to said head driving means driving pulsesobtained by delaying pulses occurring sequentially in the step pulsesignal by the predetermined length of time.
 17. An integrated circuitaccording to claim 16, wherein said head is mounted on a head carriagewhich is movable in a radial direction of the disk-shaped recordingmedium and is arranged to be driven by said stepping motor, thepredetermined length of time to be used for delaying corresponds to alength of time of a delay resulting from at least one of inertia,backlash and play existing within a part extending from said steppingmotor through said carriage, and the predetermined period of timecorresponds to a length of time necessary for said head comes to aquiescent state after a pulse in said step pulse signal causes the headto move from a track at which the head is currently located to anadjacent track on the disk-shaped recording medium.
 18. An integratedcircuit according to claim 17, wherein said driving pulse generatingmeans includes a delay circuit for delaying pulses of the step pulsesignal, a counter for deciding whether or not a pulse interval of thestep pulse signal is less than the predetermined period of time, and amultiplexer arranged to selectively perform switching, according to anoutput of said counter, between a driving pulse obtained withoutdelaying a pulse of the step pulse signal and a driving pulse obtainedthrough said delay circuit by delaying a pulse of the step pulse signalby the predetermined length of time.
 19. A disk driving device operablyresponsive to an input step pulse signal comprising a plurality ofpulses, said device comprising:a) head driving means for moving a headresponsively to driving pulses input thereto; and b) control means forreceiving said input step pulse signal and for generating said drivingpulses, said control means including first circuit means operable fordirectly inputting said pulses of said input step pulse signal to saidhead driving means, second circuit means operable for delaying saidpulses of said input step pulse signal and for inputting said delayedpulses to said head driving means, third circuit means for detectingpulse intervals of said input pulse signal, fourth circuit meansresponsive to detection by said third circuit means for selectivelyoperating said first and second circuit means and delay circuit meansfor receiving said pulses of said input step pulse signal, said delaycircuit means having a delay corresponding to a length of time of adelay resulting from at least one of inertia, backlash and play existingwithin said head driving means.